I. Field of the Invention
The present invention relates to the field of computer systems. More specifically, the present invention relates to chipsets in computer systems.
II. Background Information
A multi-processor system is a system that includes at least two processors. The at least two processors are coupled to a host bus. The host bus is typically coupled to a chipset that, among other things, may control access to a system memory. The chipset may be coupled to an input/output bus for access to input/output devices. The input/output bus may be a Peripheral Component Interconnect (PCI) bus.
There are instances when more than one processor desires to perform an access to the PCI bus. For example, assume a case where the multi-processor system included two processors, CPU1 an CPU2, and both processors want to perform a stream of write operations to the PCI bus. In these instances the system uses the chipset, that is coupled to both the host bus and to the PCI bus, in performing the series of write operations. Assuming that a particular device such as a holding buffer is used by the chipset to store portions of data to be written by one of the CPUs to the PCI. When CPU1 does a series of line-writes to PCI, the holding buffer may fill up at a certain point in time. When CPU2 initiates a write on the host bus attempting to perform a write to the PCI bus, the chipset may detect that the holding buffer is full. In this case, typically, the chipset may retry CPU2. By retrying CPU2 the chipset tells CPU2 to try the same cycle (the write cycle to the PCI bus) at a later time because the chipset is not in a position to complete the cycle at the current time. Eventually, the chipset flushes the holding buffer out to PCI thus creating space to receive more data to be written to the PCI. However, before CPU2 may initiate another write cycle, CPU1 may come back and fill up the holding buffer again. This sequence may repeat indefinitely, such that CPU2 may not be permitted access to the shared resource for a certain period of time and livelock may occur in the system.
It is desirable to provide a method and apparatus for sharing a resource in a multi-processor system where the CPUs may share a resource efficiently without being unnecessarily prevented from timely utilizing a shared resource.
The present invention provides a computer system that includes at least two host agents. The computer system further includes a chipset that includes a shared resource to be shared by the at least two host agents. The chipset prevents a first host agent, that occupies the shared resource from accessing the shared resource until the second host agent, has made progress in accessing the shared resource.